Integrated circuits are fabricated on the surface of a semiconductor wafer in layers and later singulated into individual semiconductor devices, or xe2x80x9cdies.xe2x80x9d Many fabrication processes are repeated numerous times, constructing layer after layer until fabrication is complete. Metal layers, which typically increase in number as device complexity increases, include patterns of conductive material that are vertically insulated from one another by alternating layers of insulating material. Conductive traces are also separated within each layer by an insulating, or dielectric, material. Vertical, conductive tunnels called xe2x80x9cviasxe2x80x9d typically pass through insulating layers to form conductive pathways between adjacent conductive patterns. Since the material of a semiconductor waferxe2x80x94commonly siliconxe2x80x94tends to be relatively fragile and brittle, dies are often assembled into protective housings, or xe2x80x9cpackages,xe2x80x9d before they are interconnected with a printed circuit board (PCB).
The land grid array (LGA) package is a semiconductor package wherein a die is mounted on a package substrate and enclosed by a rigid lid typically comprised of a homogenous material. The LGA package is so named because the substrate has an array of circular electrical contact pads, or xe2x80x9clands,xe2x80x9d arranged in a grid pattern on its underside. The lands are brought into electrical contact with the PCB generally by a socket having polymer interposers, metal springs or other electrically conductive element for contacting both the lands and the appropriate conductive portions of the PCB below. The LGA package is generally held in compression with the PCB by a socket, ensuring effective interconnections are maintained between the package and PCB. The die is usually connected to the substrate by a wirebonding, tape-automated bonding (TAB), or flip-chip interconnection process.
Flip-chip interconnect technology supports xe2x80x9carea array interconnection,xe2x80x9d a technology in which the die (or xe2x80x9cchipxe2x80x9d) can be mechanically and electrically connected to a substrate or board through an array of solder bumps on the active face of the die. As the entire active face of the die (and not just the periphery) can be used for interconnections, this technique increases the number of connections that can be made for a given die size. The die is affixed to the substrate facedown (or xe2x80x9cflippedxe2x80x9d) by slightly melting the solder bumps in an oven reflow process, attaching them to the substrate. The solder bump area is often reinforced by introducing an epoxy underfill between the die and the substrate in order to improve solder joint reliability. Electrical performance can also be improved by reducing inductance and capacitance, as a result of the reduced distance between the active surface of the die and the underlying board over non-flip-chip configurations.
Referring now to FIGS. 1A and 1B, a packaged semiconductor device 100 is shown as including a die 110 packaged in an LGA package 120. In the cross-sectional side view shown in FIG. 1B, the die 110 is oriented with its active (or xe2x80x9ctopxe2x80x9d) surface 112 facing down towards the package substrate 122, in a flip-chip configuration. Solder bumps 114 arranged on the active surface 112 of the die 110 are generally attached to the upper surface 124 of the substrate 122 by an oven reflow process. The lower surface 126 of the substrate 122 is populated with a grid array of electrical contact lands 128.
After the die 110 is attached to the substrate 122, an underfill material 116 may be injected under the die and around solder bumps 114 to improve the reliability of these joints. Chip capacitors 150 are commonly attached to the substrate 122 in a similar manner. A lid attach material 140, such as an epoxy or silicone, is applied to the back surface 118 of the die 110 as well as around the perimeter of the upper surface 124 of substrate 122. A rigid lid 130 in the shape of an open-ended box is then positioned open-side-down over the substrate 122, such that the inside surface 132 of the lid contacts the lid attach 140 on the inactive die surface 118. The perimeter edges 134 of the lid 130 contact the lid attach 140 on the upper surface 124 of the substrate 122, thereby forming a substantially sealed cavity 160 around the die. It should be noted that the package 120 includes the substrate 122 and lid 130, whereas the packaged semiconductor device 100 includes both the package 120 and all its constituent components, as well as the die(s) 110 mounted within the package.
When an LGA package is inserted in a socket for testing or mounting to a PCB board, the package is generally under a high compressive load. The high compressive force is required to ensure reliable electrical contact between the LGA pad and the interposer polymer-column or metal-spring bumps typically used as interconnects between the substrate and the PCB. The compressive force on an LGA package may be between 250-500 pounds (Ibf) for a typical 1500-pin package, which may only be about 4-cmxc3x974-cm in footprint area. Single-cavity-lid flip-chip assembly techniques, such as the aforementioned LGA assembly, can result in high stresses in the comparatively small die.
Referring now to FIG. 2, an exemplary LGA assembly 200 is shown in a cross-sectional view illustrating how an LGA package 120 is typically attached to a PCB 202. The LGA package 120 is interconnected with the PCB 202 by an interposer structure 210, which may include springs 212 for contacting lands on the LGA substrate 122. Compression forces maintain the connection between the package 120 and the PCB 202. A heatsink 220 is typically mounted above the package lid 130 and secured to the PCB 202 by rods 230 passing through the heatsink and PCB. The bottom ends of rods can be secured in a backing plate 240 underneath a support plate 250 on the bottom of the PCB 202. Compression forces on the package 120 can be varied by adjusting variable-stiffness springs 260 positioned above the heatsink.
In flip-chip LGA assembly, much of the compression force applied to the package tends to travel through the die, since it is generally in the center of the package and LGA assembly. Stresses within the die can lead to cracking of metallization within the die, as well as to the insulating dielectric structures positioned between the metal layers. Commonly used low-k dielectric structures may include materials with a relatively low cohesive strength, such as porous organosilicate glass (OSG). Such low-k dielectrics are used as both inter-level dielectrics (e.g., between metal layers) and inter-metal dielectrics (e.g., between metal structures within the same layer). This class of materials can have a low cohesive strength compared to adjacent metal structures, and consequently may be especially susceptible to damage from mechanical forces. Accordingly, it is preferable to distribute forces applied to the package lid to the outer edges of the lid, away from the fragile die.
Common LGA lids are homogenous structures, or composed of a single material, such as copper-tungsten (CuW). As shown by the approximate values displayed in Table 1 below, CuW has a very similar coefficient of thermal expansion (CTE) to that of alumina (Al2O3), a material commonly used in ceramic LGA packages. A goal in packaging technology is to design packages such that the interfaces of adjacent materials do not have significantly different CTE""s. As temperature variances would cause a high-CTE material to expand or contract more than a lower-CTE material, the two materials would tend to pull away from one another, or delaminate, at the common interface.
Although the CTE values of a copper-tungsten lid (xcx9c6.5 ppm/xc2x0 C.) and an alumina substrate (xcx9c6.7 ppm/xc2x0 C.) are similar, the thermal conductivity (k) of copper-tungsten is relatively moderate. A lid incorporating an area of relatively high-thermal-conductivity material over the die would allow greater heat dissipation from the die. In addition, the homogeneous copper-tungsten lid would contribute to high stresses in the silicon die under the LGA compressive loads, an undesirable trait when used over a fragile die.
It is desired to devise an LGA package lid allowing greater heat dissipation and reduced deformation under an applied load than conventional designs, while maintaining a similar CTE to that of the package substrate. Preferably, an improved LGA package design will distribute applied loads more effectively, such that loads applied to the LGA lid are transferred to the underlying structure primarily through the perimeter edges of the lid, and less through the die itself.
Disclosed are a composite lid for a semiconductor package and a method for assembling the composite lid into a packaged semiconductor device. The composite lid includes a plurality of materials, with a first material disposed over and attached to the back surface of the die with a low-modulus thermal gel and a second material disposed towards the perimeter of the lid. The second material has a modulus of elasticity greater than the modulus of elasticity of the first material, and preferably, at least twice that of the first material.
In a preferred embodiment, the first material is disposed in the central area of the composite lid, and the second material is disposed in the perimeter areas of the lid, extending substantially throughout the height of the lid. In an alternative embodiment, the first material is disposed in the central area of the composite lid, and the second material is disposed in the corner areas of the lid, extending substantially throughout the height of the lid. In a typical configuration, the die is a bumped flip-chip die interconnected to an LGA package substrate.